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1. general description the pca9701/pca9702 are low power 18 v tolerant spi general purpose input (gpi) shift register designed to monitor the status of switch inputs. it generates an interrupt when one or more of the switch inputs change state. the input level is recognized as a high when it is greater than 0.7 v dd and as a low when it is less than 0.4 v dd (minimum threshold of 2 v at 5 v node). the pca9701 can monitor up to 16 switch inputs and the pca9702 can monitor up to 8 switch inputs. the falling edge of the cs pin samples the input port status and clears the interrupt. when cs is low, the rising edge of the sclk loads the shift register and shifts the value out of the shift register. the serial input is sampled on the falling edge of sclk. each of the input ports has a 18 v breakdown esd protection circuit. when used with a series resistor (minimum 100 k w ), the input can connect to a 12 v battery and support double battery, reverse battery, 27 v jump start and 40 v load dump conditions in automotive applications. higher voltages can be tolerated on the inputs depending on the series resistor used to limit the input current. with both the high breakdown voltage and high esd, these devices are useful for both automotive (aec-q100 quali?cation available) and mobile applications. the pca9703/pca9704 are new pin compatible devices for the pca9701/pca9702 which have an interrupt masking feature allowing selected inputs to not generate interrupts and provides higher ground offset of 0.55 v dd (minimum of 2.5 v at 5 v node) with minimum hysteresis of 0.05 v dd (minimum of 225 mv at 5 v node). 2. features n 16 general purpose input ports (pca9701) or 8 general purpose input ports (pca9702) n 18 v tolerant input ports with 100 k w external series resistor n input low threshold 0.4 v dd with minimum of 2 v at v dd = 4.5 v n open-drain interrupt output n interrupt enable pin (int_en) disables interrupt output n v dd range: 2.5 v to 5.5 v n i dd is very low 2.5 m a maximum n spi serial interface with speeds up to 5 mhz n aec-q100 quali?cation available n esd protection exceeds 8 kv hbm per jesd22-a114, 350 v mm per aec-q100, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int rev. 03 3 december 2008 product data sheet
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 2 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int n operating temperature range: - 40 c to +125 c n pca9701 offered in so24, tssop24 and hwqfn24 packages n pca9702 offered in tssop16 package 3. applications n body control modules n switch monitoring n industrial equipment n cellular telephones n emergency lighting n sbc wake pin extension 4. ordering information [1] pca9701pw/q100 is aec-q100 compliant. contact i2c.support@nxp.com for ppap. table 1. ordering information type number topside mark package name description version pca9701d pca9701d so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1 pca9701hf 9701 hwqfn24 plastic thermal enhanced very very thin quad ?at package; no leads; 24 terminals; body 4 4 0.75 mm sot994-1 pca9701pw pca9701pw tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 pca9701pw/q100 [1] pca9701/q tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 pca9702pw pca9702 tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 3 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 5. block diagram (1) n = 15 for pca9701; n = 7 for pca9702 fig 1. block diagram of pca9701; pca9702 cs sclk sdin sdout int 002aac422 shift register dff0 in0 dff1 in1 dffn (1) inn (1) pca9701/pca9702 v ss v dd int_en input status register 20 m a
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 4 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 6. pinning information 6.1 pinning fig 2. pin con?guration for so24 fig 3. pin con?guration for tssop24 fig 4. pin con?guration for hwqfn24 fig 5. pin con?guration for tssop16 sdout v dd int sdin int_en sclk in0 cs in1 in15 in2 in14 in3 in13 in4 in12 in5 in11 in6 in10 in7 in9 v ss in8 pca9701d 002aac636 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 pca9701pw pca9701pw/q100 sdout v dd int sdin int_en sclk in0 cs in1 in15 in2 in14 in3 in13 in4 in12 in5 in11 in6 in10 in7 in9 v ss in8 002aac424 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 002aad050 pca9701hf transparent top view in11 in4 in5 in12 in3 in13 in2 in14 in1 in15 in0 cs in6 in7 v ss in8 in9 in10 int_en int sdout v dd sdin sclk terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19 pca9702pw sdout v dd sdin int_en sclk in0 in1 in7 in2 in6 in3 in5 v ss in4 002aac425 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 int cs
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 5 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 6.2 pin description [1] hwqfn24 package die supply ground is connected to both v ss pin and exposed center pad. v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. table 2. pin description symbol pin type description so24, tssop24 hwqfn24 tssop16 sdout 1 22 1 output 3-state serial data output; normally high-impedance int 2 23 2 output open-drain interrupt output (active low) int_en 3 24 3 input interrupt output enable 1 = interrupt is enabled 0 = interrupt is disabled and high-impedance in0 4 1 4 input input port 0 in1 5 2 5 input input port 1 in2 6 3 6 input input port 2 in3 7 4 7 input input port 3 in4 8 5 9 input input port 4 in5 9 6 10 input input port 5 in6 10 7 11 input input port 6 in7 11 8 12 input input port 7 v ss 12 9 [1] 8 ground ground supply in8 13 10 - input input port 8 in9 14 11 - input input port 9 in10 15 12 - input input port 10 in11 16 13 - input input port 11 in12 17 14 - input input port 12 in13 18 15 - input input port 13 in14 19 16 - input input port 14 in15 20 17 - input input port 15 cs 21 18 13 input chip select (active low) sclk 22 19 14 input serial input clock sdin 23 20 15 input serial data input (20 m a pull-down) v dd 24 21 16 supply supply voltage
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 6 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 7. functional description pca9701 is a 16-bit general purpose input (gpi) with an open-drain interrupt output designed to monitor switch status. by putting an external 100 k w series resistor at the input port, the device allows the input to tolerate momentary double 12 v battery, reverse battery, 27 v jump start or 40 v load dump conditions. the interrupt output is asserted when an input port status changes. the open-drain interrupt output is enabled when int_en is high and disabled when int_en is low. the input port status is accessed via the 4-wire spi interface. the pca9702 is the 8-bit version of the pca9701. multiple pca9701 or pca9702 devices can be serially connected for monitoring a large number of switches by connecting the sdout of one device to the sdin of the next device. sclk and cs must be common among all devices and interrupt outputs may be tied together. no external logic is necessary because all the devices interrupt outputs are open-drain that function as wired-and and can simply be connected together to a single pull-up resistor. 7.1 spi bus operation the pca9701 or pca9702 interfaces with the controller via the 4-wire spi bus that is comprised of the following signals: chip select ( cs), serial clock (sclk), serial data in (sdin), and serial data out (sdout). to access the device, the controller asserts cs low, then sends sclk and sdin. when reading/writing is complete, the controller de-asserts cs. see figure 6 for register access timing. 7.1.1 cs - chip select the cs pin is the device chip select and is an active low input. the falling edge of cs captures the input port status in the input status register. if the interrupt output is asserted, the falling edge of cs will clear the interrupt. when cs is low, the spi interface is active. when cs is high, the spi interface is disabled. 7.1.2 sclk - serial clock input sclk is the serial clock input to the device. it should be low and remain low during the falling and rising edge of cs. when cs is low, the ?rst rising edge of sclk parallel loads the shift register from the input. the subsequent rising edges on sclk serially shifts data out from the shift register. the falling edge of sclk samples the data on sdin. 7.1.3 sdin - serial data input sdin is the serial data input port. the data is sampled into the shift register on the falling edge of sclk. sdin is only active when cs is low. this input has a 20 m a pull-down current source. 7.1.4 sdout - serial data output sdout is the serial data output signal. sdout is high-impedance when cs is high and switches to low-impedance after cs goes low. when cs is low, after the ?rst rising edge of sclk the most signi?cant bit in the shift register is presented on sdout. subsequent rising edges of sclk shift the remaining data from the shift register onto sdout.
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 7 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 7.1.5 register access timing figure 6 shows the waveforms of the device operation. initially cs is high and sclk is low. on the falling edge of cs, input port status, data[n:0] is captured into the input status register, and subsequently the ?rst rising edge of sclk parallel loads the shift register. the falling edge of sclk samples the data on the sdin. the msb from the shift register is valid and available on the sdout after the ?rst rising edge of sclk. 7.2 interrupt output int is the open-drain interrupt output and is active low. a pull-up resistor of approximately 10 k w is recommended. the interrupt output is asserted when the input status is changed, and is cleared on the falling edge of cs or when the input port status matches the input status register. when there are multiple devices, the int outputs may be tied together to a single pull-up. t ab le 3 illustrates the state of the interrupt output versus the state of the input port and input status register. the interrupt output is asserted when the input port and input status register differ. data[n:0] is data on the input pins, in[n:0]. for 8-bit gpi (pca9702), n = 7; for 16-bit gpi (pca9701), n = 15. shaded areas indicate active but invalid data. fig 6. register access timing cs sclk sdin sdout high-impedance msb in msb out 002aac426 msb - 1 in msb - 1 out lsb in lsb out input status register shift register data[n:0] data[n:0] sample sdin
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 8 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int [1] input status register is the value or content of the d ?ip-?ops. [2] logic states shown for int pin assumes 10 k w pull-up resistor. 7.3 general purpose inputs the general purpose inputs (gpi) are designed to behave like a typical input in the 0 v to 5.5 v range, but are also designed to have low leakage currents at elevated voltages. the input structure allows for elevated voltages to be applied through a series resistor. the series resistor is required when the input voltage is above 5.5 v. the series resistor is required for two reasons: ?rst, to prevent damage to the input avalanche diode, and second, to prevent the esd protection circuitry from creating an excessive current ?ow. the esd protection circuitry includes a latch-back style device, which provides excellent esd protection during assembly or typical 5.5 v applications. the series resistor limits the current ?owing into the part and provides additional esd protection. the limited current prevents the esd latch-back device from latching back to a low voltage, which would cause excessive current ?ow and damage the part. the minimum required series resistance for applications with input voltages above 5.5 v is 100 k w . for applications requiring an applied voltage above 27 v, equation 1 is recommended to determine the series resistor. failure to include the appropriate input series resistor may result in product failure and will void the warranty. (1) the series resistor should be placed physically as close as possible to the connected input to reduce the effective node capacitance. the input response time is effected by the rc time constant of the series resistor and the input node capacitance. table 3. interrupt output function truth table h = high; l = low; x = dont care int_en input port status input status register [1] int output [2] hl l h hl h l hh l l hh h h lx x h r s voltage applied 17 v C i i ------------------------------------------------------------ =
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 9 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 7.3.1 v il , v ih and switching points a minimum low threshold of 2.0 v is guaranteed for the logical switching points for the inputs. see figure 7 for details. the v il is speci?ed as a maximum of 0.40 v dd and is 2.0 v at 4.5 v v dd . this means that if the user applies 2.0 v or less to the input (with v dd = 4.5 v), or as the voltage passes this threshold, they will always see a low. the v ih is speci?ed as a minimum of 0.7 v dd . this means that if the user applies 3.15 v or more to the input (with v dd = 4.5 v), or as the voltage passes this threshold, they will always see a high. fig 7. logic level thresholds for general purpose inputs 002aae128 v i v dd hysteresis minimum 0 v 0.4v dd 0.7v dd high low v ih v il possible ground shift
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 10 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 8. application design-in information 8.1 general application 8.2 automotive application supports: ? 12 v battery (8 v to 16 v) ? double battery (16 v to 32 v) ? reverse battery ( - 8 v to - 16 v) ? jump start (27 v for 60 seconds) ? load dump (40 v) (1) n = 15 for pca9701; n = 7 for pca9702 fig 8. typical application cs sclk sdin sdout 002aac423 in0 in1 inn (1) pca9701/ pca9702 v ss v dd int_en int controller or processor 10 k w 2.5 v to 5.5 v 1.5 k w 100 k w relay 18 v 100 k w 18 v 10 k w 5 v 500 k w 180 v 50 k w in2 open
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 11 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 8.2.1 sbc wake port extension with cyclic biasing system basis chips (sbc) offer many functions needed for in-vehicle networking solutions. some of the features built into sbc are: ? transceivers (hs-can, lin 2.0) ? scalable voltage regulators ? watchdog timers; wake-up function ? fail-safe function for more information on sbc, refer to http://www .nxp .com/inde x.html#/pip/pip=[pfp=53482]|pp=[t=pfp ,i=53482] . 8.2.1.1 uja106x with pca9701, standby ? pca970x ?ts to sbc uja106x and uja107x family ? pca970x can be powered by v1 of sbc ? extends the sbc with 8/16 additional wake inputs ? m c can be set to stop-mode during standby to save ecu standby current. sbc with gpi periodically monitors the wake inputs C cyclic bias via v3 C very low system current consumption even with clamped switches fig 9. uja106x with pca9701 with supplied m c (standby) cs sdin sdout sclk 002aae016 in0 pca9701 v ss v dd int_en int in1 in15 alternate pvr100ad-b5v0 v3 uja106x wake v1 gnd v cc m c csn mosi miso sclk gnd
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 12 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 8.2.1.2 uja106x with pca9701, sleep ? very low quiescent system current (50 m a) due to disabled m c and cyclically biasing of switches ? wake-up upon change of switches or upon bus traf?c (can and lin) ? pca970x supplied out of cyclically biased transistor regulator fig 10. uja106x with pca9701 with unsupplied m c (sleep) cs sdin sdout sclk 002aae017 in0 pca9701 v ss v dd int_en in1 in15 alternate pvr100ad-b5v0 v3 uja106x wake v1 gnd v cc m c csn mosi miso sclk gnd int alternate pmem4010nd rstn alternate pdtc144tu
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 13 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 8.2.1.3 uja107x with pca9701, standby ? uja107x sbc provides wbias pin for cyclic biasing of the inputs ? compatible with uja107x based assps 8.2.2 application examples including switches to battery fig 11. uja107x with pca9701 with supplied m c (standby) cs sdin sdout sclk 002aae018 in0 pca9701 v ss v dd int_en int in1 in15 alternate pdta144eu bat uja107x wake v1 gnd v cc m c csn mosi miso sclk gnd wbias bat fig 12. clamp 15 (ignition) detection fig 13. switches to battery and ground with cyclic biasing 002aae019 in0 pca9701 in1 in15 switch bias clamp 15 002aae020 in0 pca9701 in1 in15 switch bias bat bat
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 14 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 9. limiting values [1] with gpi external series resistors, the inputs support double battery, reverse battery and load dump conditions. during double battery or load dump the input pin will drain slightly higher leakage current until the input drops to 18 v. for more detail of leakage cur rent speci?cation, please refer to t ab le 5 static char acter istics . see section 7.3 for series resistor requirements. [2] n = 15 for pca9701; n = 7 for pca9702. table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). t amb = - 40 c to +125 c, unless otherwise speci?ed. symbol parameter conditions min max unit v dd supply voltage - 0.5 +6.0 v i i input current in[n:0] pins with series resistor and v i > 5.5 v, [1] [2] - 350 m a v i input voltage gpi pins in[n:0]; no series resistor [1] [2] - 0.5 +6 v spi pins - 0.5 +6 v t stg storage temperature - 65 +150 c t j(max) maximum junction temperature operating - 125 c
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 15 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 10. static characteristics [1] v dd must be lowered to 0.2 v for at least 5 m s in order to reset device. [2] minimum v il is 2.0 v at v dd = 4.5 v. [3] for gpi pin voltages > 5.5 v, see section 7.3 . table 5. static characteristics v dd = 2.5 v to 5.5 v; v ss =0v; t amb = - 40 c to +125 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v dd supply voltage 2.5 3.3 5.5 v i dd supply current v dd = 5.5 v; inpu t=5vor18v; int_en = v dd - 1.0 2.5 m a v por power-on reset voltage [1] - 1.8 2.2 v general purpose inputs v il low-level input voltage [2] - - 0.4v dd v v ih high-level input voltage 0.7v dd -- v i i input current gpi recommended maximum current; v i > 5.5 v; with series resistor r s [3] - - 100 m a i ih high-level input current each input; v i =v dd - 1- +1 m a i li input leakage current v i = 17 v; 100 k w series resistor - 1- +1 m a c i input capacitance v i =v ss or v dd - 2.0 5.0 pf interrupt output i ol low-level output current v dd = 4.5 v; v ol = 0.4 v 6 - - ma v dd = 2.5 v; v ol = 0.4 v 3 - - ma i oh high-level output current v oh =v dd - 1- +1 m a c o output capacitance - 2 5 pf spi and control v il low-level input voltage - - 0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i ih high-level input current sdin; v i =v dd = 5.5 v - 20 40 m a i ol low-level output current sdout; v ol = 0.4 v v dd = 4.5 v 5 - - ma v dd = 2.5 v 3 - - ma i oh high-level output current sdout; v oh =v dd - 0.5 v v dd = 4.5 v 5 - - ma v dd = 2.5 v 3 - - ma c i input capacitance v i =v ss or v dd -25pf c o output capacitance sdout; cs = v dd -46pf
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 16 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 11. dynamic characteristics table 6. dynamic characteristics v dd = 2.5 v to 5.5 v; v ss =0v; t amb = - 40 c to +125 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit f max maximum input clock frequency - - 5 mhz t r rise time sdout; 10 % to 90 % at 5 v - 35 60 ns t f fall time sdout; 90 % to 10 % at 5 v - 25 50 ns t wh pulse width high sclk 50 - - ns t wl pulse width low sclk 50 - - ns t spilead spi enable lead time cs falling edge to sclk rising edge 50 - - ns t spilag spi enable lag time sclk falling edge to cs rising edge 50 - - ns t su(sdin) sdin set-up time sdin to sclk falling edge 20 - - ns t h(sdin) sdin hold time from sclk falling edge 30 - - ns t en(sdout) sdout enable time from cs low to sdout low-impedance; figure 17 --55ns t dis(sdout) sdout disable time from rising edge of cs to sdout high-impedance; figure 17 --85ns t v(sdout) sdout valid time from rising edge of sclk; figure 18 --55ns t su(sclk) sclk set-up time sclk falling to cs falling 50 - - ns t h(sclk) sclk hold time sclk rising after cs rising 50 - - ns t por power-on reset pulse time time before cs is active after v dd >v por - - 250 ns t rel(int) interrupt release time after cs going low; figure 19 - - 500 ns t v(int_n) valid time on pin int after inn changes or int_en goes high - - 100 ns fig 14. timing diagram cs sclk sdin sdout int t spilag t wl t wh high-impedance t spilead msb in msb out 002aac428 t su(sdin) t h(sdin) t en(sdout) t v(sdout) t dis(sdout) t rel(int) 50 % 50 % t su(sclk) t h(sclk)
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 17 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int fig 15. ac waveform for t por timing fig 16. ac waveform for int timing cs sclk sdout msb out 002aad158 t por v por 2.5 v 0 v v dd msb - 1 cs inn int_en 002aad159 t rel(int) state 0 state 1 state 0 int t v(int_n) t v(int_n) t rel(int)
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 18 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 12. test information r l = load resistance. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 17. test circuitry for enable/disable times, sdout (t en(sdout) and t dis(sdout) ) fig 18. test circuitry for switching times, sdout (t v(sdout) ) fig 19. test circuitry for switching times, int pulse generator v o c l 50 pf r l 10 k w 002aac580 r t v i v dd dut v dd open 10 k w pulse generator v o c l 50 pf 002aac581 r t v i v dd dut pulse generator v o c l 50 pf r l 10 k w 002aac582 r t v i v dd dut v dd
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 19 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 13. package outline fig 20. package outline sot137-1 (so24) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1 99-12-27 03-02-19
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 20 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int fig 21. package outline sot355-1 (tssop24) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 112 24 13 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 a max. 1.1
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 21 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int fig 22. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 22 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int fig 23. package outline sot994-1 (hwqfn24) references outline version european projection issue date iec jedec jeita sot994-1 - - - mo-220 - - - sot994-1 07-02-07 07-03-03 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. unit a (1) max mm 0.8 0.05 0.00 0.30 0.18 4.1 3.9 2.25 1.95 4.1 3.9 2.25 1.95 2.5 2.5 0.1 a 1 dimensions (mm are the original dimensions) hwqfn24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm 0 2.5 5 mm scale b c 0.2 d (1) d h e (1) e h e 0.5 e 1 e 2 l 0.5 0.3 v w 0.05 y 0.05 y 1 0.1 b a terminal 1 index area e d detail x a a 1 c b e 2 e 1 e e 1/2 e 1/2 e a c b ? v m c ? w m terminal 1 index area 6 13 12 7 18 24 19 1 l e h d h c y c y 1 x
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 23 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 24 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 14.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 24 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 7 and 8 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 24 . table 7. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 8. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 25 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 15. abbreviations msl: moisture sensitivity level fig 24. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 9. abbreviations acronym description assp application speci?c standard product can controller area network cdm charged-device model dut device under test ecu electronic control unit esd electrostatic discharge gpi general purpose input hbm human body model hs-can high-speed controller area network lin local interconnect network lsb least signi?cant bit mm machine model msb most signi?cant bit pcb printed-circuit board ppap production part approval process rc resistor-capacitor network sbc system basis chip spi serial peripheral interface m c microcontroller
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 26 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 16. revision history table 10. revision history document id release date data sheet status change notice supersedes pca9701_pca9702_3 20081203 product data sheet - pca9701_pca9702_2 modi?cations: ? section 1 gener al descr iption : C 1 st paragraph, 3 rd sentence: appended (minimum threshold of 2 v at 4.5 v node) C 3 rd paragraph, 2 nd sentence changed from ... reverse battery, and load dump conditions to ... reverse battery, 27 v jump start and 40 v load dump conditions C 4 th paragraph: added (aec-q100 quali?cation available) C added (new) 5 th paragraph ? section 2 f eatures : C added (new) 3 rd bullet item C 10 th bullet: deleted int_en is 7.5 kv; changed from 600 v mm per jeds22-a115 to 350 v mm per aec-q100 ? section 3 applications : added new 1 st and 6 th bullets ? t ab le 1 order ing inf or mation : C added type number pca9701pw/q100 C added t ab le note [1] and its reference ? section 7 functional descr iption , 1 st paragraph, 2 nd sentence changed from ... reverse battery, or load dump conditions to ... reverse battery, 27 v jump start or 40 v load dump conditions ? t ab le 3 interr upt output function tr uth tab le : int column: appended output to column heading; changed high-z to h (3 places); added t ab le note [2] and its reference ? added section 7.3.1 v il , v ih and s witching points ? section 8 application design-in inf or mation : C figure 8 t ypical application moved to (new) section 8.1 gener al application C added section 8.2 ? t ab le 5 static char acter istics : C sub-section general purpose inputs: v il max value changed from 0.3v dd to 0.4v dd ; added (new) t ab le note [2] C sub-section general purpose inputs: c i typ value changed from 1.0 pf to 2.0 pf; c i max value changed from 2.5 pf to 5.0 pf C sub-section interrupt output: changed c o max value from 4 pf to 5 pf C sub-section spi and control: c i max value changed from 4 pf to 5 pf C t ab le note [1] : added phrase for at least 5 m s ? figure 15 a c w a v ef or m f or t por timing modi?ed ? updated soldering information pca9701_pca9702_2 20070829 product data sheet - pca9701_pca9702_1 pca9701_pca9702_1 20070323 objective data sheet - -
pca9701_pca9702_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 3 december 2008 27 of 28 nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 17.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 17.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 18. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pca9701; pca9702 18 v tolerant spi 16-bit/8-bit gpi with int ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 3 december 2008 document identifier: pca9701_pca9702_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 spi bus operation . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 cs - chip select. . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.2 sclk - serial clock input. . . . . . . . . . . . . . . . . . 6 7.1.3 sdin - serial data input . . . . . . . . . . . . . . . . . . 6 7.1.4 sdout - serial data output . . . . . . . . . . . . . . . 6 7.1.5 register access timing . . . . . . . . . . . . . . . . . . . 7 7.2 interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.3 general purpose inputs . . . . . . . . . . . . . . . . . . 8 7.3.1 v il , v ih and switching points. . . . . . . . . . . . . . . 9 8 application design-in information . . . . . . . . . 10 8.1 general application. . . . . . . . . . . . . . . . . . . . . 10 8.2 automotive application . . . . . . . . . . . . . . . . . . 10 8.2.1 sbc wake port extension with cyclic biasing . 11 8.2.1.1 uja106x with pca9701, standby . . . . . . . . . . 11 8.2.1.2 uja106x with pca9701, sleep. . . . . . . . . . . . 12 8.2.1.3 uja107x with pca9701, standby . . . . . . . . . . 13 8.2.2 application examples including switches to battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 10 static characteristics. . . . . . . . . . . . . . . . . . . . 15 11 dynamic characteristics . . . . . . . . . . . . . . . . . 16 12 test information . . . . . . . . . . . . . . . . . . . . . . . . 18 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 14 soldering of smd packages . . . . . . . . . . . . . . 23 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 23 14.2 wave and re?ow soldering . . . . . . . . . . . . . . . 23 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23 14.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 24 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 27 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 17.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 18 contact information . . . . . . . . . . . . . . . . . . . . 27 19 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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